Floorplanning is the process of choosing the best grouping and connectivity of logic in a design, and of manually placing blocks of logic in an FPGA, where the goal is to increase density, routability, or performance. The intent is to reduce route delays for selected logic by suggesting a better placement. A good floorplanning methodology can improve performance and help the placed and routed design meet timing.
Prof. Santambrogio and Prof. Miele, in the context of their PhD course “Advanced Topic on Heterogeneous Computing System” are organising, with Marco Rabozzi, the first Floorplanner Design Contest at Politecnico di Milano. Students attending the course are invited to participate, but participation is not mandatory.
The design contest will open on the 6th of December and will close on the 19th of December at noon (strict submission deadline). During this period of time, participants will have the chance to attend some special tutoring sessions.
Each project / entry for the contest has to be realized by a single participant.
The floorplanning design contest platform can be accessed at the following link: http://floorplanning-contest.necst.it/
|Date||Time||Room (@ Politecnico)||Topic|
|6th of December||2pm - 5pm||Seminar Room @ Building 20, DEIB||Introduction to FPGA Floorplanning and the design contest|
|12nd of December||9am - 12pm||Basemenet @ Building 20, NECSTLab Meeting Room||Tutoring session|
|14th of December||1pm - 3pm||Basemenet @ Building 20, NECSTLab Meeting Room||Tutoring session|
The two winners of the contest will be selected for attending RAW workshop at IPDPS conference in Vancouver (21st - 22nd of May 2018) and in joining the NECSTLab delegation to attend the NECST Group Conference in San Francisco (22nd of May - 3rd of June 2018).