Hack @ NECST Events

Xilinx PYNQ Hackathon (XPH)    

The Xilinx PYNQ Hackathon is a 48h no-stop competition where participants are going to develop their ideas on the brand-new PYNQ platform.

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized - powering industry advancements in Cloud Computing, Embedded Vision, Industrial IoT, and 5G. For more information, visit www.xilinx.com.

Tower of Hanoi (ToH)  

Badass students doing things on their PCs? Check. Soulless coding monkeys solving security challenges? Check. Handsome Italian guys better than Gordon Ramsey? Check. Perfectly and lovely written write-ups? Check. Sounds perfect. Tower of Hanoi (also known as Hanoiati) is the Politecnico di Milano CTF team.

Cool... but what is a CTF? CTFs (Capture The Flag) are information security competitions, aimed at teaching how to find, exploit and patch security vulnerabilities and, in turn, how to avoid vulnerabilities when writing software.

Sport and Wellness Hackathon    

The Sport and Wellness Hackathon is a 48 hours' event organized by NECST Laboratory in partnership with Iterpro, an Italian startup aiming at filling the gap between practice and sports science, in order to turn data into action and help football clubs to make better decision faster.

From November to January students will have the opportunity to learn how to use the main technology (hardware and software) that will be available during the hackathon. In February participants, will be selected into max 25 teams (max 5 students per team) and the hackathon will take place during the first weekend of March.

At the end of the hackathon each team will be asked to deliver the proof of concept of their project. 5 selected teams will attend the final event at the end of May. The final event will take place at the headquarter of a very important sport company.

Floorplanning Design Contest  

Floorplanning is the process of choosing the best grouping and connectivity of logic in a design, and of manually placing blocks of logic in an FPGA, where the goal is to increase density, routability, or performance. The intent is to reduce route delays for selected logic by suggesting a better placement. A good floorplanning methodology can improve performance and help the placed and routed design meet timing.

Prof. Santambrogio and Prof. Miele, in the context of their PhD course “Advanced Topic on Heterogeneous Computing System” are organising, with Marco Rabozzi, the first Floorplanner Design Contest at Politecnico di Milano. Students attending the course are invited to participate, but participation is not mandatory.

The design contest will open on the 6th of December and will close on the 19th of December. During this period of time, participants will have the chance to attend some special tutoring sessions.

SDAccel Design Contest  

Data center operators constantly seek more server performance. Currently they develop applications with easy-to-program multicore CPUs and GPUs but CPU performance/watt is hitting the wall and GPU performance/watt is hitting the wall as well. Designers working on high-volume data-center applications want GPU ease-of-programming but with hardware that will give them low power consumption, high throughput, and the lowest possible latency. However, there’s a significant problem with scalability of multicore-CPU and GPU accelerators: developers would like to target simple full height plug-in PCIe boards to use as application accelerators in data center servers.

FPGAs provide the heart of what’s needed for power-efficient hardware application acceleration on one chip while providing solutions that are below the 25W per board targets. The SDAccel development environment for OpenCL, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx family, combines the industry's first architecturally optimising compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

At NECSTLab we are organising the first SDAccel Design Contest, which will take place during the second semester. During this period of time, participants will have the chance to attend some special tutoring sessions on SDAccel.